(1) Field of the Invention
The present invention relates to cost reduction in the assembly of semiconductor devices and shortening of time necessary for developing semiconductor devices.
(2) Disclosure of Related Art
Size reduction and functional enhancement are required of various types of electronic equipment such as cellular phones and digital still cameras. With such requirements, advanced packaging techniques compatible with size reduction, increase in processing speed and increase in the number of pins of semiconductor devices are demanded. In particular, because of remarkable progress in size reduction of semiconductor chips and increase in the number of pins using system-on-a-chip (SOC) technology, it is necessary to reduce the distance between pads (terminals) on a semiconductor chip. In the assembly of a semiconductor device, pads closely provided on a semiconductor chip need to overlap pads provided on a board when viewed from above.
In a package which uses a multi-layer board of an organic material and is often used for system large scale integration (LSI) incorporated in equipment such as cellular phones and digital still cameras, if the distance between pads (terminals) on a semiconductor chip is smaller than that in conventional devices, it is difficult to form wiring in the board such that the pads on the board overlap the closely-located pads on the semiconductor chip. Thus, in such a case, an expensive special board is needed.
To solve this problem, a currently-promising approach is a two-level connection that connects a board and a semiconductor chip through an intermediate wiring layer such as a silicon interposer. Specifically, the semiconductor chip and the silicon interposer are placed such that pads provided on the semiconductor chip at a pitch finer than that in conventional devices overlap pads on the silicon interposer. The silicon interposer includes not only the pads connected to the pads on the semiconductor chip but also pads provided at a larger pitch than the pads connected to the semiconductor chip. These pads provided at a larger pitch are connected to pads on the board.
As another example of using a silicon interposer, Japanese Laid-Open Patent Publication No. 2001-257307 discloses that a silicon interposer is used as a re-wiring layer in order to increase the number of possible combinations of sizes of semiconductor chips to be laminated. In this manner, the structures of packages have advanced from a conventional structure in which a package is composed of a semiconductor chip and a board to a structure in which an intermediate wiring layer is added between a semiconductor chip and a board.
Semiconductor devices are also required to meet the following demands.
Equipment such as cellular phones takes much time and cost for development of software associated with system LSI. Thus, it is important how a plurality of types of semiconductor devices are fabricated using one semiconductor chip (system LSI), i.e., how a semiconductor chip is shared. In this circumstance, it is necessary to differentiate a function of a semiconductor device by changing only the type or arrangement of peripheral components such as a memory capacitor using a single semiconductor chip. In this case, the arrangement of solder balls (i.e., portions to which signals are transmitted) in a semiconductor device is changed according to a change of the type or arrangement of peripheral components. Since there were not many demands for conventional semiconductor devices, it is more effective to change the wiring layout of a board than to use an intermediate wiring layer as disclosed in Japanese Laid-Open Patent Publication No. 2001-257307 in changing the type or arrangement of peripheral components. However, in recent years, only the change of a wiring layout of a board at every change of the type or arrangement of peripheral components cannot meet the increasing demands for current semiconductor devices.